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These are the user uploaded subtitles that are being translated: 1 00:00:01,520 --> 00:00:08,000 hi there this is grant jennings from goin  semiconductor and today i'm going to walk through   2 00:00:08,000 --> 00:00:14,880 our usb solutions and roadmap and particularly  talk about a new solution that we have which is   3 00:00:14,880 --> 00:00:23,840 a usb 2.05 capable of high speed interfacing  at 480 megabits per second for the usb 2 spec   4 00:00:24,800 --> 00:00:32,640 this is a one of a kind solution you know no other  fpga company in the world has it has ever done it   5 00:00:32,640 --> 00:00:41,760 and so we're very excited at going for it being  the innovative fpga semiconductor company so let's   6 00:00:41,760 --> 00:00:49,680 get started the agenda here is we're going to go  through just a brief overview to kind of align   7 00:00:49,680 --> 00:00:56,480 everybody on goin products so i'm just gonna give  a very brief overview of gohan's product portfolio   8 00:00:57,200 --> 00:01:04,400 and then i'm going to talk about new products  and solutions coming soon then we'll go into some   9 00:01:04,400 --> 00:01:09,680 focused usb solution discussions and an  update there and we'll go a little bit   10 00:01:09,680 --> 00:01:17,360 deeper into our usb 2.0 solutions including  the phi as well as the link layer or sie   11 00:01:17,360 --> 00:01:24,560 as it's called in the usb specification and  then we'll go into a usb solution road map   12 00:01:25,360 --> 00:01:32,480 this is just kind of where now that we have usb  2.0 and you're capable of using it on any go on   13 00:01:32,480 --> 00:01:40,320 fpga what are some of the demos and solutions that  will be coming available in the months to come and   14 00:01:40,320 --> 00:01:47,520 the rest of this year and then we'll go into some  use case examples uh we'll talk about development   15 00:01:47,520 --> 00:01:54,320 boards and how you can actually and your customers  can actually test out the usb 2.0 solution   16 00:01:55,520 --> 00:02:01,760 and then we'll go into uh where you can get  some support for for go and design services   17 00:02:02,480 --> 00:02:07,840 and uh just a little bit of some links to  some other resources that may be useful   18 00:02:08,560 --> 00:02:16,240 so let's get started uh first let's go into the  product summary and i tried to just keep that this   19 00:02:16,240 --> 00:02:25,120 we have other slides that you may have seen from  sales that kind of go through a table of different   20 00:02:25,120 --> 00:02:32,000 capabilities but i wanted to keep it really  simple as of today we have two product families   21 00:02:32,000 --> 00:02:39,520 a non-volatile family and a volatile fpga family  family so non-volatile it has embedded flash   22 00:02:39,520 --> 00:02:47,520 typically smaller density great for interfacing  and bridging type applications we also have you   23 00:02:47,520 --> 00:02:53,280 know devices with some extra capabilities but  this is all in the 1 to 20k lookup table range   24 00:02:53,840 --> 00:03:00,080 um so before it was 1 to 10k it's actually a new  device that pushes us up to the 20k range which is   25 00:03:00,800 --> 00:03:08,720 pretty unique in uh in the market right now  then traditional fpgas we have a 20 to 55k   26 00:03:08,720 --> 00:03:16,160 lookup table range a little bit higher  performance fabric more io and uh you   27 00:03:16,160 --> 00:03:21,040 know some other capabilities that are not on  the non-volatile but you don't get the flash   28 00:03:21,840 --> 00:03:30,480 so then within that one of the unique things about  going semiconductor is our hybrid fpgas so if you   29 00:03:30,480 --> 00:03:39,840 see in the part number an s that means that it has  an embedded hardened cortex m3 hardcore processor   30 00:03:41,280 --> 00:03:47,520 if you see an r in the product name that means  that it has an embedded extended user memory   31 00:03:48,320 --> 00:03:55,760 and it can be around 4 to 16 megabytes depending  on the device chosen it could have varying bus   32 00:03:55,760 --> 00:04:04,640 widths and it could be varying types of memory  it can be psram sdram or ddr so you can choose   33 00:04:04,640 --> 00:04:10,160 the right type of memory for your application  you can also have extended embedded user flash   34 00:04:11,040 --> 00:04:18,320 e-series is our security fpgas and these  have a puff based embedded security   35 00:04:19,360 --> 00:04:26,880 core within them and that basically means that  the key generation is asynchronous key generation   36 00:04:26,880 --> 00:04:32,720 and the keys are generated at power  up based on sram puff technology   37 00:04:34,320 --> 00:04:42,320 and then we have rf series um gw1 rf series so  if you see a rf in the series name that's an   38 00:04:42,320 --> 00:04:51,680 fpga plus a hardened mcu and plus a bluetooth low  energy transceiver 5.0 to be specific so hopefully   39 00:04:51,680 --> 00:04:59,200 that just that's pretty much going semiconductor  product line from the devices in a nutshell   40 00:05:00,960 --> 00:05:05,520 so now we're going to talk about new and  upcoming semiconductor products so these   41 00:05:05,520 --> 00:05:17,520 are new devices that are either here now or uh  coming soon so first we have the gw2 an 18x so   42 00:05:17,520 --> 00:05:25,120 this is an 18k uh it's actually 20k um the the  titles the part number's a little deceiving   43 00:05:25,120 --> 00:05:31,280 so there's a few extra luts but around a 20k  lookup table device um that's non-volatile   44 00:05:32,320 --> 00:05:41,200 and it has very fast boot up um from the  embedded flash it has embedded security   45 00:05:41,200 --> 00:05:48,640 so it has the puff base security and it also has  pin compatibility to other semiconductor devices   46 00:05:50,560 --> 00:05:56,400 then we have the gw1n2 now this is a 2k  non-volatile device and the key thing about   47 00:05:56,400 --> 00:06:06,960 it is that it has two gigabit per second rx and  tx mippy d5 hardcores so you have true mippy rx   48 00:06:06,960 --> 00:06:12,720 at up to two gigabits per second and the speed  on that we know at least uh two and we're   49 00:06:12,720 --> 00:06:19,760 working to to get a little bit more using the  pre-emphasis capability and then on the tx side   50 00:06:19,760 --> 00:06:29,280 you have true uh slvs 200 high speed and 1.2 volt  low power mode capabilities to provide a true   51 00:06:30,240 --> 00:06:37,760 mippy d5 interface so that's really good and also  those uh one and two i believe that there are some   52 00:06:37,760 --> 00:06:42,160 r series of that so if you need some frame  buffering in there this device is really for   53 00:06:42,160 --> 00:06:51,600 video bridging and uh video interfacing as well as  some processing and you know it's pretty common to   54 00:06:51,600 --> 00:06:56,720 sometimes need a frame buffer in those use cases  so the r series is available for that as well   55 00:06:58,560 --> 00:07:05,920 automotive devices so we have our first automotive  devices and we have a 1k non-volatile as well as a   56 00:07:05,920 --> 00:07:16,560 20k volatile fpga to kind of cover the automotive  space and these devices are aec100q qualify   57 00:07:18,000 --> 00:07:25,200 assps so this is something new to go in but  we have a series of application specific chips   58 00:07:25,200 --> 00:07:34,480 coming out um the first round of them is really  specific to usb to another interface bridging for   59 00:07:34,480 --> 00:07:40,320 basically programmer cables and programming  so we have a usb to j tag we have a usb to spy   60 00:07:40,320 --> 00:07:47,440 we have a usb to ur and we have a usb to  is i2c assp so you can look forward to that   61 00:07:48,960 --> 00:07:56,160 you know there are some of these bridging chips  that are readily available particularly like usb   62 00:07:56,160 --> 00:08:03,040 to uart just due to programming microcontrollers  but other cases like usb to jtag usb to spy   63 00:08:03,040 --> 00:08:10,800 and usb to ic there's a lot fewer solutions  on the market and as a result the devices   64 00:08:10,800 --> 00:08:16,000 are a little bit more expensive so we  think that our assps provide a really   65 00:08:16,000 --> 00:08:22,240 good um affordable and competitive  competitive solution in the market um   66 00:08:22,240 --> 00:08:28,800 and so we're really excited about that and  then the last um you know kind of updated   67 00:08:28,800 --> 00:08:36,080 product um silicon product update is that is the  x series so we have several devices that provide   68 00:08:36,080 --> 00:08:44,480 pin for pin compatibility to devices that are  either ended end of life long lead time or um   69 00:08:45,280 --> 00:08:50,960 for customers that are using an existing device  but would like to add some new features some new   70 00:08:50,960 --> 00:08:58,400 capabilities and they need larger density but  also pin compatibility really is helpful to them   71 00:09:00,000 --> 00:09:07,600 i need to make one more product update  regarding a legacy device the gw1ns2   72 00:09:07,600 --> 00:09:14,000 this is different than the gw1n2 that is just  being released with the hardened d5 cores   73 00:09:14,640 --> 00:09:26,400 the gw1 and s2 was a 2k lookup table fpga with  hardened cortex m3 and hardened usb 2.0 phi   74 00:09:27,600 --> 00:09:33,120 this device has had some issues related  to the foundry that it was fabricated on   75 00:09:33,680 --> 00:09:42,560 all of our production devices are fabbed on tsmc  however this other device was was fabricated at a   76 00:09:42,560 --> 00:09:49,840 different foundry and that led to some issues  so it's been kind of still on the roadmap to   77 00:09:50,720 --> 00:09:57,040 get it working and it still technically is however  one of the major things that's broken on it is the   78 00:09:57,040 --> 00:10:07,760 usb 2.0 hard fi in 2.0 mode and we after that  we released a gw1 and s4 which still has the   79 00:10:07,760 --> 00:10:16,560 hardened cortex m3 but it doesn't have the usb 2.0  hard fi and then now we have the usb 2.0 software   80 00:10:16,560 --> 00:10:25,200 which works just as well so there's a good chance  that the gw1 and s2 will be discontinued because   81 00:10:25,200 --> 00:10:34,800 we have the 4k which is an overall lower  cost but more resource intensive device   82 00:10:35,600 --> 00:10:43,680 and we have the usb 2.0 software solution which  can be used on all of the current go and devices   83 00:10:44,320 --> 00:10:50,960 so it's very likely that we will discontinue that  device as the two features are already covered in   84 00:10:50,960 --> 00:11:01,360 a broader spectrum with the tsmc foundry devices  so that's kind of updated semiconductor products   85 00:11:01,360 --> 00:11:07,360 um from going let's let's go into uh some  solutions update so this is not all of the   86 00:11:07,360 --> 00:11:13,280 solutions that are kind of coming down the  pipeline but it's a few that i thought were   87 00:11:13,280 --> 00:11:21,360 notable there's several solutions going on  right now it's pretty exciting what has been   88 00:11:22,480 --> 00:11:28,720 being developed with our devices and  how much they've matured and advanced   89 00:11:30,640 --> 00:11:36,880 over the last you know few years so  first is a foc motor control ip solution   90 00:11:37,920 --> 00:11:45,040 so this is an industrial motor control  solution providing high precision and parallel   91 00:11:45,040 --> 00:11:51,280 feedback loops for controlling multiple motors you  can show one more or two but one of the you know   92 00:11:52,560 --> 00:12:01,120 situations that our customers tend to gravitate  towards this solution over other motor control   93 00:12:01,120 --> 00:12:06,960 solutions is when they run into an issue where  they need to either increase the number of   94 00:12:06,960 --> 00:12:13,280 i o that the cpu have and particularly  the the types of interfaces so the adcs   95 00:12:14,640 --> 00:12:26,560 and some of the gpios and encoder links like rs485  i believe they need to increase the number of   96 00:12:26,560 --> 00:12:34,000 of interfaces for multiple motors and then  also the cpu needs to increase in performance   97 00:12:34,000 --> 00:12:42,880 to accommodate these motors and typically the  cpu has to kind of dedicate itself to to the to   98 00:12:42,880 --> 00:12:48,880 each individual motor and give it with a real-time  operating system give it preference and priority   99 00:12:48,880 --> 00:12:54,720 because if you start running some other  application it starts bogging down the system and   100 00:12:54,720 --> 00:12:59,840 you don't have a real-time operating system your  motors could start slowing down and going all over   101 00:12:59,840 --> 00:13:10,640 the place so what the fpga solution provides is an  fpga either in between the cpu and the motors or   102 00:13:10,640 --> 00:13:18,800 the mosfet drivers or you can actually embed the  cpu inside the fpga and have a one chip solution   103 00:13:18,800 --> 00:13:27,120 what whatever your preference is um but each motor  control loop runs it completely independently and   104 00:13:27,120 --> 00:13:35,040 that we provide an api for the cpu to call each  of the current control loop modules so this way   105 00:13:35,040 --> 00:13:42,080 there's no no bog down on the cpu and the motors  can run independently and when you need to make   106 00:13:42,080 --> 00:13:49,040 an adjustment that api call just adjusts that  motor and that current control loop in the fpga   107 00:13:49,040 --> 00:13:58,960 so it's very um good solution and provides a lot  of higher precision control at a i would say a   108 00:14:00,400 --> 00:14:09,120 much more cost-efficient overall bomb solution  we also have a simple motor control ip this is   109 00:14:09,120 --> 00:14:14,880 for doing just very simple  motors like maybe in toys or   110 00:14:16,480 --> 00:14:22,960 consumer applications and we actually have this on  the gw1 and rf so you can actually control a motor   111 00:14:22,960 --> 00:14:30,240 through bluetooth low energy or multiple motors  for smaller motors for consumer applications so   112 00:14:30,240 --> 00:14:38,800 that's pretty unique and pretty interesting then  we have go ai 2.0 which is our machine learning   113 00:14:39,440 --> 00:14:48,400 inference and npu solution and hardware ip so we  have several new demonstrations that have come out   114 00:14:48,400 --> 00:14:55,920 over the last year person detection car detection  digit detection analog meter detection multiple   115 00:14:56,560 --> 00:15:06,320 digit detection different input sources so you  know different cameras different hdmi inputs audio   116 00:15:07,920 --> 00:15:16,560 audio classification gesture control several  demos and there's there's some next generation   117 00:15:16,560 --> 00:15:22,400 stuff coming that you can look forward to on that  basically mainly around improving performance   118 00:15:23,760 --> 00:15:28,160 but i would assume some additional  demos that you can look forward to there   119 00:15:29,360 --> 00:15:38,400 and then lastly the image signal processor ip so  this is if you're if you're not aware when you   120 00:15:38,400 --> 00:15:45,040 have a system with an image processor sorry  when you have a system with an image sensor   121 00:15:45,760 --> 00:15:49,360 a lot of times there is not an image  processor built into that image sensor   122 00:15:50,240 --> 00:15:57,840 so the data that you get from the image sensor is  just raw pixel data and that pixel data needs to   123 00:15:57,840 --> 00:16:05,680 be processed using an image signal processor now a  lot of times this is built into an soc or you know   124 00:16:05,680 --> 00:16:12,080 a larger processor device there are dedicated  image signal processors as well but if you're   125 00:16:12,080 --> 00:16:20,000 doing any sort of image processing on fpga you  need a in a lot of cases you need a image signal   126 00:16:20,000 --> 00:16:27,040 processor pipeline if you want the image to look  good some cases you don't need it um you know if   127 00:16:28,240 --> 00:16:34,720 like in the case of go ai if you if you train the  model to accommodate that that you could remove   128 00:16:34,720 --> 00:16:39,520 those resources and not need the image processor  but in a lot of cases if you're going to output   129 00:16:39,520 --> 00:16:44,240 that image and use it for something or display  that image coming from the camera you need an   130 00:16:44,240 --> 00:16:52,000 image signal processing pipeline to make the image  look correct so that's a great new additional iep   131 00:16:52,880 --> 00:17:04,640 and then the usb 1.1 2.0 and the phi and the sie  so already in ipcor generator within gohan eda   132 00:17:05,200 --> 00:17:15,520 there's a sie or link layer for usb 1.1  and usb 2.0 and you can either use that sie   133 00:17:15,520 --> 00:17:27,120 with an external usb 1.1 or 2.05 or an internal  usb 1.0 or 2.05 also within goin ip core generator   134 00:17:27,680 --> 00:17:39,120 we have a usb 1.1 phi and you can use this on  virtually any of the ios available on any of the   135 00:17:39,120 --> 00:17:50,000 goin devices and so you can instantiate a usb 1.15  inside the fpga providing a you know link layer   136 00:17:50,000 --> 00:17:56,560 with the sie and the phi for 1.1 which is  capable of about 12 megabits per second   137 00:17:58,000 --> 00:18:04,880 lastly what i'm going to go into more detail  is usb 2.0 which is capable of 480 megabits per   138 00:18:04,880 --> 00:18:11,920 second and this is a really challenging ip to do  and that this is why it hasn't been done before   139 00:18:13,040 --> 00:18:21,840 it involves clock data recovery at 480 megabits  which is kind of too low for a lot of the   140 00:18:23,200 --> 00:18:32,960 embedded certes type fpgas but also too fast to  just use gearboxes with over sampling and so we   141 00:18:32,960 --> 00:18:43,520 have a you know we've built a solution around a  recovery method for the megabit signaling using f   142 00:18:44,080 --> 00:18:54,800 gowen's dedicated high-speed i o capabilities and  features and that's a patented solution that we're   143 00:18:54,800 --> 00:19:03,760 really excited about because we've had a number of  requests for usb 2.0 interfacing but haven't been   144 00:19:03,760 --> 00:19:09,120 able to service them and nobody's really in the  market has been able to service them until now so   145 00:19:09,120 --> 00:19:16,960 please reach out to your customers if you've had a  customer that has talked about usb and needing usb   146 00:19:16,960 --> 00:19:24,400 on their products uh we've got we've got the  solution for them and we would really like to   147 00:19:24,400 --> 00:19:32,080 engage and you know make some opportunities  happen with either usb 1.1 or usb 2.0 148 00:19:34,560 --> 00:19:45,360 so the usb 2.0 you know the launch  of usb 2.0 phi is on around may 15th   149 00:19:45,360 --> 00:19:52,320 of 2021 and you'll probably be seeing this  presentation around then so at that time the   150 00:19:52,320 --> 00:20:01,120 latest version of going eda with ipcor generator  will have the usb 2.0 softfi available for use   151 00:20:01,120 --> 00:20:09,920 in in the eda tool so it's already ready to go and  you can virtually again with a few limitations on   152 00:20:09,920 --> 00:20:20,400 the 2.0 because you need to use the the high speed  io but virtually any io any fpga that gowan has an   153 00:20:20,400 --> 00:20:28,720 offering for you can use the usb 2.0 software so  you can have multiple usb 2.05 no problem there   154 00:20:30,240 --> 00:20:38,080 so here's a little bit more focused update going  is now a member of the usb implementers forum and   155 00:20:38,080 --> 00:20:46,240 we have 1.1 and 2.0 solutions so 12 megabits  per second and 480 megabits per second 1.1   156 00:20:46,240 --> 00:20:54,480 is still used a lot for control and just basic  communications and actually usb 1.1 is kind of   157 00:20:54,480 --> 00:21:02,000 included with 2.0 so so 2.0 is actually capable  of a 12 megabit mode and a 480 megabit mode   158 00:21:02,000 --> 00:21:08,960 usb 2 generally has applications that are more  data transfer specific since the data rate is up   159 00:21:10,160 --> 00:21:20,160 um so in ipcor generator we have all  these ips the 1.15 2.05 1.1 and 2.0 sie   160 00:21:20,960 --> 00:21:27,920 and it's kind of defaulted to a virtual com port  scenario but you can use it for other things   161 00:21:28,560 --> 00:21:34,240 we just use that example because it's uh we like  the virtual com port because there are native   162 00:21:34,240 --> 00:21:43,040 drivers within windows 10 windows 7 windows 10 and  linux that makes it very easy to just get started   163 00:21:43,040 --> 00:21:49,680 and i'll explain a little bit more about that  later we also have a usb type-c power delivery   164 00:21:49,680 --> 00:21:54,720 solution and so you can actually you know if  you have customers that are interested in us   165 00:21:55,280 --> 00:22:03,040 usb or usb type-c you can actually combine these  ips together for uh you know a total usb solution   166 00:22:04,480 --> 00:22:10,240 and then lastly we support primarily  just out of the box the virtual comport   167 00:22:11,040 --> 00:22:16,800 type solution because again it's the the  driver capability makes it very easy to use   168 00:22:17,360 --> 00:22:24,320 however there are other device types being  explored like video over usb things like that   169 00:22:25,520 --> 00:22:33,360 and that will just basically as as the solutions  build there will be more um more device types   170 00:22:33,360 --> 00:22:38,320 and you can program these for different  device types that the si is fully programmable   171 00:22:38,320 --> 00:22:44,960 so lots of good opportunities  there for new and unique solutions 172 00:22:48,320 --> 00:22:56,160 okay so now uh we're going to go into just  specifically usb 2.0 finesse ie so this is again   173 00:22:56,160 --> 00:23:03,760 a brand new solution to the fpga market previously  before this solution that only gowan has   174 00:23:03,760 --> 00:23:12,960 you had to use an external phi to interface a  separate chip to interface the uh to interface usb   175 00:23:12,960 --> 00:23:19,040 2.0 with an fpga and there's a patent  pen pending implementation for this   176 00:23:20,080 --> 00:23:24,800 that is uniquely capable on gowen's  high speed and flexible fpga i o   177 00:23:26,240 --> 00:23:32,640 supported in all going devices um with exception  to the 1nz which is our ultra low power device   178 00:23:32,640 --> 00:23:39,360 it has overall lower performance so  that just due to its low power and   179 00:23:39,360 --> 00:23:47,600 so that one's not supported but everything else  is and then devices can support as many usb 2.0   180 00:23:47,600 --> 00:23:56,880 interfaces as the i o permits so that means that  you can do things like a usb hub uh you could do   181 00:23:56,880 --> 00:24:06,400 a hub of you know usb to pcie you could or you  could do or sorry excuse me a pci you could do a 182 00:24:09,440 --> 00:24:17,840 you know you could do the the possibilities are  pretty much endless you can do microphone to usb   183 00:24:18,560 --> 00:24:28,480 you could do multiple microphones to usb you could  do um usb to device to usb host you could do hsic   184 00:24:28,480 --> 00:24:39,840 to usb there are many options and this is just  an interface to allow customers to be creative   185 00:24:39,840 --> 00:24:47,840 with whatever they want to build so now  i'm going to go into usb 2.0 phi and sie   186 00:24:48,480 --> 00:25:00,560 just some information related to it so the usb  2.0 and 1.05 run at 60 megahertz this is native to   187 00:25:01,120 --> 00:25:07,600 the deserialization process and the over sampling  process that's pretty common with all usb   188 00:25:09,040 --> 00:25:18,960 utmi interface fis as well as the sies and  then just 2.0 runs faster so 480 megabits   189 00:25:19,760 --> 00:25:27,120 and usb 1.1 at 12 megabits the resources for  the 2.0 are a little bit larger just under 2k   190 00:25:27,120 --> 00:25:34,640 lookup tables so this can fit in as small as a  2k device and uses five block ram versus the 1.1   191 00:25:34,640 --> 00:25:40,160 solution which is three block ram so you know i  just mentioned this so if you have like a really   192 00:25:40,160 --> 00:25:48,240 tight or cost you know sensitive solution we have  a we've had a lot of customers before we even had   193 00:25:48,240 --> 00:25:58,480 the usb 2.0 solution they would come to us and  say i need a usb 2.0 solution and a lot of them   194 00:25:59,120 --> 00:26:05,440 as we started to communicate with them they  just needed a usb 2.0 solution for basic control   195 00:26:05,440 --> 00:26:13,040 and communication they didn't need the full 480  megabits and there are some i o advantages and   196 00:26:13,040 --> 00:26:20,640 some resource advantages to the 1.1 solution so if  you just need 12 megabits go with the 1.1 solution   197 00:26:20,640 --> 00:26:28,240 don't don't go beyond that and so i would say a  lot of there is a lot of customer opportunity just   198 00:26:28,240 --> 00:26:35,280 for the usb 1.1 solution and then if you need the  extra bandwidth 2.0 is available and this is just   199 00:26:35,280 --> 00:26:44,720 a block diagram of what um what the fi and the sae  look like you know if you were to place both ips   200 00:26:44,720 --> 00:26:53,200 in the fpga and we do have a reference design for  this and basically the phi and the usb sie talk   201 00:26:53,200 --> 00:26:59,200 over a utmi plus interface which is the common  interface between the phi and the link layer 202 00:27:02,400 --> 00:27:12,320 okay usb solution roadmap so 1.1 is available  now 2.05 is just released and these are the   203 00:27:12,320 --> 00:27:21,440 eda numbers that it should be the sie for 2.0 and  1.1 is available now we have reference designs   204 00:27:21,440 --> 00:27:32,480 for virtual com ports virtual com port device id  and then we have a video video over usb solution   205 00:27:32,480 --> 00:27:38,240 that we're working on and then you can expect  other protocols and other examples to follow   206 00:27:39,280 --> 00:27:49,280 we also are working on a csi2 mipi csi2 camera to  usb 2 reference design so this should be pretty   207 00:27:49,280 --> 00:27:56,240 unique and pretty cool kick off about for this  is mid main you should expect it sometime in q3   208 00:27:56,880 --> 00:28:10,400 we also have an hsic reference design in progress  so hsic is basically usb 2.0 for inside inside   209 00:28:10,400 --> 00:28:18,400 embedded devices so it's basically kind of like  usb 2 but inside like let's say a pc and the   210 00:28:18,400 --> 00:28:24,720 benefit of using hsic is that it provides a clock  lane so you don't need the clock data recovery   211 00:28:25,840 --> 00:28:31,520 so it's kind of similar to like mipi csi 2 if  you're familiar with that protocol or maybe dsi or   212 00:28:31,520 --> 00:28:44,880 maybe d5 and this provides both a power and a cost  and a ease of use benefit for situations inside   213 00:28:44,880 --> 00:28:52,720 on on ship or on the board so that's it's used  for things like inside a pc however once you go   214 00:28:52,720 --> 00:29:01,520 outside the pc and you're going over a cable you  can't really send a clock and data over wire pairs   215 00:29:01,520 --> 00:29:09,440 over a cable things get out of alignment and even  if you have alignment capabilities there can be   216 00:29:11,040 --> 00:29:19,840 you know uh issues with the uh the peak to peak  voltage being reduced and things like that so you   217 00:29:19,840 --> 00:29:26,160 need a little bit more advanced recovery system  and so it's best to use fewer wires which just   218 00:29:26,160 --> 00:29:33,120 makes the cable cheaper and embed the  clock within the data which also helps   219 00:29:33,120 --> 00:29:39,840 with the voltage levels um if the data basically  in the when the when the clock is encoded   220 00:29:40,640 --> 00:29:47,600 in the data the way that it's encoded means that  there's an equal balance of zeros and ones which   221 00:29:47,600 --> 00:29:53,120 means that the peak-to-peak voltage doesn't drift  and that's that's the benefit and that's why   222 00:29:54,640 --> 00:30:02,000 we typically use embedded clock on  cable interfacing so but there's a   223 00:30:02,000 --> 00:30:09,360 lot of opportunities for going from hsic for  communication inside on the pcb and then going   224 00:30:09,360 --> 00:30:14,480 out on a cable with usb 2.0 and so that's  exactly why we're building that reference design 225 00:30:17,280 --> 00:30:27,920 so mainly on the usb sie side we have the  device side so it's just a more popular use case   226 00:30:27,920 --> 00:30:37,040 however we have basically for our testing purposes  we have the the code to do a host solution as well   227 00:30:37,600 --> 00:30:41,280 so this would be you'd use the  same fi but you'd be able to do   228 00:30:42,480 --> 00:30:49,280 a host link layer and communicate with usb devices  so this in progress is a little further out but   229 00:30:49,280 --> 00:30:58,080 q4 around that time frame of this year please  let me know if you see any usb 1.1 or 2.0 host   230 00:30:58,880 --> 00:31:03,520 solution needs and we can communicate  and talk about that and see   231 00:31:03,520 --> 00:31:08,320 see make sure we understand their needs and make  sure it's aligned with that target completion date   232 00:31:10,160 --> 00:31:18,480 lastly we have an mjpeg encoder and this is  in progress uh you know sometime around the q4   233 00:31:18,480 --> 00:31:28,480 time range this is needed for things like uh  the csi2 to usb solution um or it may be so   234 00:31:28,480 --> 00:31:32,080 we have it kind of on the roadmap that  it's something that we'd like to do we see   235 00:31:32,080 --> 00:31:37,840 you know some need and if you see any  you know use cases or opportunities there   236 00:31:39,040 --> 00:31:45,680 related or not related to usb please let  us know and we will try to understand those   237 00:31:45,680 --> 00:31:51,120 customers needs as best as possible and  adjust our solution roadmap accordingly   238 00:31:52,880 --> 00:31:59,520 and then also the bridging assps which i talked  about earlier these are application specific chips   239 00:31:59,520 --> 00:32:09,360 that just do the function they do so usb  to jtag usb to spy usb to i2c usb to ur and   240 00:32:09,360 --> 00:32:18,960 i2s audio to and from usb you can expect these  around the q3 time frame and they're they're   241 00:32:18,960 --> 00:32:24,880 currently in testing and so i think that that  that's where on the timeframe will be available   242 00:32:26,880 --> 00:32:32,000 okay so now i'm going to go into use cases now i  have to make it clear that some of these are will   243 00:32:32,000 --> 00:32:38,960 be available and some of them are just theoretical  use cases to start engaging with customers um the   244 00:32:38,960 --> 00:32:48,560 big feat has been conquered which was to get the  usb 1.1 and 2.0 solutions available but now we're   245 00:32:48,560 --> 00:32:54,560 gonna go into you know what you could use it for  and some of these are built like the example here   246 00:32:54,560 --> 00:33:08,080 for usb bridging so usb to jtag usb to spy usb  to i2c usb to ur and i2s audio to and from usb   247 00:33:08,960 --> 00:33:16,400 so yeah this is just a high level diagram of those  same use cases as the assp but we also have them   248 00:33:16,400 --> 00:33:23,840 in fpga solutions as well in case a customer wants  to expand add some buffering some extra features 249 00:33:25,920 --> 00:33:35,280 another usb example is the usb sorry csi2 to usb  solution so here's a diagram of that and then also   250 00:33:36,000 --> 00:33:42,720 usb to dsi so let's say you have a small display  and you want to interface to that display over   251 00:33:43,840 --> 00:33:50,480 over usb that's also possible and that solution  we don't have you know it's not on the roadmap but   252 00:33:50,480 --> 00:33:55,600 if you if you see a customer that is interested  in that we can certainly discuss that with them 253 00:33:59,280 --> 00:34:08,000 okay usb to bluetooth examples so going to or  from bluetooth low energy since we have the gw1 rf   254 00:34:08,000 --> 00:34:16,800 device you can definitely make a usb to bluetooth  low energy dongle so that's pretty unique and this   255 00:34:16,800 --> 00:34:21,440 solution is is not something that's on the roadmap  but would be actually fairly straightforward to   256 00:34:21,440 --> 00:34:26,480 put together i think so please let us know  if you see any opportunities in this area 257 00:34:29,840 --> 00:34:36,880 data and storage buffering so sorry data  shortage and buffering these are just a couple   258 00:34:37,520 --> 00:34:45,040 kind of high-level solution ideas so the one  on the left the diagram on the left is showing   259 00:34:46,000 --> 00:34:52,800 basically using the embedded user flash of the  little b product family the non-volatile family   260 00:34:53,360 --> 00:35:01,200 and use utilizing that that internal flash to  connect to usb 2.0 and so this could be used for   261 00:35:01,760 --> 00:35:06,000 let's say security dongles where you may have some   262 00:35:06,000 --> 00:35:12,880 some key pair in the flash you could also  use this with our secure fpga solution   263 00:35:13,760 --> 00:35:21,040 and this would basically provide a non-volatile  region that you could access over usb 2.0   264 00:35:22,560 --> 00:35:28,000 and then on the right side this is  taking advantage of the extended ps ram   265 00:35:28,880 --> 00:35:34,000 devices the r series devices i mentioned earlier  and it's just showing that you know you got four   266 00:35:34,000 --> 00:35:40,480 to eight megabytes of extended ps ram memory in  the fpga you could also interface to external   267 00:35:40,480 --> 00:35:47,840 memories with the goin device like ddr and you  could have some input data you could buffer it   268 00:35:47,840 --> 00:35:54,240 and then read it out of usb2 at your own pace  or time depending on the application so this is   269 00:35:54,240 --> 00:36:01,040 pretty interesting could be very useful for data  acquisition like data acquisition cards if you've   270 00:36:01,040 --> 00:36:07,280 got you know a bunch of wires monitoring some  system you can store it and then buffer it out   271 00:36:08,960 --> 00:36:13,760 have it buffered and then read  it out on the pc win as needed 272 00:36:17,840 --> 00:36:23,680 this is kind of another idea of a traffic monitor  kind of similar to the data buffering case   273 00:36:24,240 --> 00:36:27,840 where um you basically just have   274 00:36:27,840 --> 00:36:36,320 a usb to usb passthrough but then you can monitor  the usb traffic and particular usb data and   275 00:36:36,320 --> 00:36:43,120 this can be you know really useful as as  a usb snooper line snooper and in fact   276 00:36:43,120 --> 00:36:51,440 you know i use this a lot during deep when i  was debugging um or testing the usb 2.0 solution   277 00:36:52,320 --> 00:37:02,080 but um this can uh you you don't even need  to build a gui for this um you can actually   278 00:37:02,080 --> 00:37:12,160 just use goin's gau going analyzer oscilloscope  so it's our built-in fpga logic analyzer you can   279 00:37:12,160 --> 00:37:19,200 just use that to monitor the data and actually  record it and save it to a file so for you know   280 00:37:19,200 --> 00:37:26,320 debugging solutions traffic monitoring solutions  over usb 2.0 this is a great uh offering 281 00:37:29,600 --> 00:37:35,840 so lastly is kind of the the multi-port hub  concept so as i mentioned you can have multiple   282 00:37:36,560 --> 00:37:44,320 usb phi interfaces and so using the host solution  that's on the roadmap along with the device   283 00:37:44,320 --> 00:37:51,760 solution this allows you to do usb hub and one  thing i left out is there's also opportunity to do   284 00:37:52,800 --> 00:38:01,280 usb hsic for the device interface and then go  out to multiple usb hosts as well so true usb   285 00:38:01,920 --> 00:38:08,000 hub chip and you can make all of the  virtual types of channels and that you want 286 00:38:11,040 --> 00:38:18,000 okay so those are my my kind of high level use  case get your ideas flowing examples and now   287 00:38:18,000 --> 00:38:23,840 i'll talk a little bit about how you can actually  have customers test these examples and get started   288 00:38:24,560 --> 00:38:30,400 so um the the usb 2.0 solution as  well as the 1.1 solution are are   289 00:38:30,960 --> 00:38:39,520 very um robust at this point i feel and uh we  do have a production board that is actually our   290 00:38:39,520 --> 00:38:46,720 dk start gw2a18 board that has been modified  just one of the connectors has been removed   291 00:38:47,600 --> 00:38:53,840 and it's been replaced with the usb 2.0 port  running to the fpga and you can do usb 2.0 or   292 00:38:53,840 --> 00:39:00,000 1.1 with this right now the board is in very  limited supply because we had just our first   293 00:39:00,000 --> 00:39:07,200 test run of the boards but it does work and if you  know there is a high customer need we can get you   294 00:39:07,200 --> 00:39:13,280 one of those boards temporarily and then we have  production availability of that this board around   295 00:39:13,280 --> 00:39:20,080 june 15th so you can expect it on the website  you can expect it um through your distribution 296 00:39:23,520 --> 00:39:29,520 abilities to obtain it and then uh there  also is another internal board that has   297 00:39:29,520 --> 00:39:36,480 just arrived internally and i there is limited  supply but it's another option the nice thing   298 00:39:36,480 --> 00:39:42,560 about this board is that it has a little b and  aurora device on it so if you have a customer   299 00:39:42,560 --> 00:39:50,640 that may want to focus on little b um we're doing  that validation as well this board is also in very   300 00:39:50,640 --> 00:39:56,240 limited supply but we can make exceptions  for particular opportunities that may arise 301 00:39:59,600 --> 00:40:11,200 so in addition to all of this we're building up  the go in design services capabilities um a lot   302 00:40:11,920 --> 00:40:20,400 and so going i call it gds and we're kind of  expanding on this is going design services   303 00:40:20,400 --> 00:40:26,800 it's our applications engineering team providing  design services for customers that want to build   304 00:40:27,680 --> 00:40:34,080 application specific solutions and  they need some design consultations to   305 00:40:34,080 --> 00:40:41,360 get them there maybe they're not so familiar with  fpgas maybe they're a little uncomfortable because   306 00:40:41,360 --> 00:40:46,960 they've never used going fpgas before and they  need a little it could be as simple as just hand   307 00:40:46,960 --> 00:40:52,800 holding some some support to get started it could  be as extreme as doing the whole design for them   308 00:40:52,800 --> 00:41:02,560 and so we're building up a platform to provide  this capability so providing custom application   309 00:41:02,560 --> 00:41:07,680 specific design consultation and providing  hardware as a service is what we like to call it   310 00:41:08,240 --> 00:41:16,000 and uh so as of right now you can it's you  will see this expanding over the next year   311 00:41:16,000 --> 00:41:21,520 but for now we're just basically going  through the info at go on semi email and so   312 00:41:21,520 --> 00:41:26,720 any potential design requests you want to submit  you can either submit them to your go in sales   313 00:41:28,080 --> 00:41:35,840 sales director directly or you can send them  through info go on semi.com you can also just   314 00:41:35,840 --> 00:41:44,400 send them to me i have no problem with that and uh  you can also you know i just put the distribution   315 00:41:44,400 --> 00:41:52,400 page which has access to um you know many of the  distributors and reps that may also be able to   316 00:41:52,400 --> 00:41:58,800 community support you or at least i put  this here just in case this presentation   317 00:41:59,520 --> 00:42:07,040 has a derivative customer facing presentation  and this would provide them the access point to   318 00:42:07,680 --> 00:42:16,960 communicate with you the distributors or the reps  and then for any design service just be ready to   319 00:42:16,960 --> 00:42:22,320 provide us the following we're going to be asking  for it if you send us an email without it so   320 00:42:22,320 --> 00:42:27,520 we need to know the design requirements as  detailed as you can possibly do and one thing   321 00:42:27,520 --> 00:42:33,440 that's very very very helpful that is a lot of  times missing is a technical block diagram if   322 00:42:33,440 --> 00:42:38,560 you can draw a block diagram of it it provides  us a picture of what you want it's very helpful   323 00:42:39,520 --> 00:42:45,200 also you know on the design requirements one  thing that can sometimes be missing as the speeds   324 00:42:45,200 --> 00:42:52,000 that things need to run at that's also useful and  anything you can provide a little bit at a higher   325 00:42:52,000 --> 00:42:58,560 level about the application like if it's using  2.0 what is it interfacing too is it a computer   326 00:42:59,360 --> 00:43:03,840 what kind of data are they going to send things  like that the more information the better   327 00:43:04,640 --> 00:43:12,640 projected volume is really important for us  because it helps us determine our nre structure so   328 00:43:14,480 --> 00:43:18,400 i don't think most customers don't have a problem  with what they're projecting if you could provide   329 00:43:18,400 --> 00:43:26,400 that that would be great and then estimated nre  budget for design development so we really want   330 00:43:26,400 --> 00:43:35,680 to get into the habit of asking this question  because it's often not asked and then it becomes   331 00:43:35,680 --> 00:43:44,960 you know potentially an issue later so you know  you we've got a customer opportunity it comes   332 00:43:44,960 --> 00:43:52,080 into sales we have apps engineers that spend time  to research and and and understand the solution   333 00:43:52,080 --> 00:43:56,880 that needs to be developed and maybe does some  pre-development to make sure that we can do it   334 00:43:57,440 --> 00:44:03,440 and then they come back and say yep we can do it  um how big is the volume you know if the volume   335 00:44:03,440 --> 00:44:11,360 is small then uh we request the nre and the  customer i think feels kind of um a little bit   336 00:44:12,000 --> 00:44:19,680 uh blindsided at that point so we i just  appreciate if we can get into the habit of just   337 00:44:19,680 --> 00:44:26,000 asking um you know do you have an nre estimate  for doing this design for you and if you know if   338 00:44:26,000 --> 00:44:30,160 there's hesitation we say well based on the volume  you know we might not even need it or based on the   339 00:44:30,160 --> 00:44:37,040 roadmap it might be already something we're doing  but we do need to ask because we do spend a lot   340 00:44:37,040 --> 00:44:44,880 of r d budget to to develop these designs and  sometimes you know plans change projects change   341 00:44:45,440 --> 00:44:52,640 so if you could help us help you by just asking  this question up front it'd be very helpful 342 00:44:55,280 --> 00:45:00,560 and then other resources so if you're new  to usb or want to understand more educate   343 00:45:00,560 --> 00:45:09,280 yourself i highly recommend this usb made simple  website it is great it goes through usb 1.1   344 00:45:09,280 --> 00:45:15,280 2.0 it goes through things that i always refer  back to it there's things that i still don't   345 00:45:15,280 --> 00:45:20,960 know about usb and it is on the site so i highly  recommend it if customer has some questions or   346 00:45:20,960 --> 00:45:27,920 you know thoughts it's a great great site to  utilize also the usb 2.0 specification itself   347 00:45:27,920 --> 00:45:34,640 itself is available for free and the usb utmi  interface specification is also available   348 00:45:36,160 --> 00:45:43,120 there are some things i will say that the usb utmi  interface that's the interface between the phi   349 00:45:43,120 --> 00:45:50,960 and the link layer that are discussed in the utmi  specification that i feel are vague in the 2.0   350 00:45:50,960 --> 00:45:58,560 specification and vice versa so um i would if you  know i would provide both um to your customer at   351 00:45:58,560 --> 00:46:04,240 the same time and if you're educating yourself  i would look at both and then below i just have   352 00:46:04,240 --> 00:46:10,320 the social media pages for going something that  your customers can reference i do intend to make a   353 00:46:10,320 --> 00:46:18,640 customer friendly version of this presentation and  video so um that's kind of why it's there and you   354 00:46:18,640 --> 00:46:25,680 can expect that there will probably be some usb  demo videos available and there also is a quick   355 00:46:25,680 --> 00:46:37,360 start guide for the dkstart uh dk dkstar ar18 usb  board so that's a starter guide that allows you to   356 00:46:38,720 --> 00:46:49,440 do a virtual com port data loop so you send data  to the host and then you receive it back and then   357 00:46:49,440 --> 00:46:55,200 it also if you press numbers it will light up  leds so if you press numbers on the keyboard   358 00:46:55,200 --> 00:47:01,360 it will light up a corresponding led and then also  if you push push buttons on the board it will send   359 00:47:01,360 --> 00:47:08,240 a message back to the pc so pretty basic but  pretty cool demo and that's all running at 2.0   360 00:47:09,200 --> 00:47:12,800 and that you could also do it with  1.1 we're not pushing the performance   361 00:47:13,440 --> 00:47:19,440 the performance is native to the protocol when  you're in each mode so basically if you go into   362 00:47:19,440 --> 00:47:26,960 2.0 the packets just transfer faster that's it  for me i hope this was useful please let me know   363 00:47:26,960 --> 00:47:32,080 what i could add or subtract particularly for  the customer facing presentation version of   364 00:47:32,080 --> 00:47:39,040 this and i look forward to helping you go in  by programming for the future thanks a lot 48320

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