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hi there this is grant jennings from goin
semiconductor and today i'm going to walk through
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our usb solutions and roadmap and particularly
talk about a new solution that we have which is
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a usb 2.05 capable of high speed interfacing
at 480 megabits per second for the usb 2 spec
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this is a one of a kind solution you know no other
fpga company in the world has it has ever done it
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and so we're very excited at going for it being
the innovative fpga semiconductor company so let's
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get started the agenda here is we're going to go
through just a brief overview to kind of align
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everybody on goin products so i'm just gonna give
a very brief overview of gohan's product portfolio
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and then i'm going to talk about new products
and solutions coming soon then we'll go into some
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focused usb solution discussions and an
update there and we'll go a little bit
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deeper into our usb 2.0 solutions including
the phi as well as the link layer or sie
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as it's called in the usb specification and
then we'll go into a usb solution road map
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this is just kind of where now that we have usb
2.0 and you're capable of using it on any go on
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fpga what are some of the demos and solutions that
will be coming available in the months to come and
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the rest of this year and then we'll go into some
use case examples uh we'll talk about development
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boards and how you can actually and your customers
can actually test out the usb 2.0 solution
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and then we'll go into uh where you can get
some support for for go and design services
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and uh just a little bit of some links to
some other resources that may be useful
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so let's get started uh first let's go into the
product summary and i tried to just keep that this
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we have other slides that you may have seen from
sales that kind of go through a table of different
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capabilities but i wanted to keep it really
simple as of today we have two product families
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a non-volatile family and a volatile fpga family
family so non-volatile it has embedded flash
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typically smaller density great for interfacing
and bridging type applications we also have you
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know devices with some extra capabilities but
this is all in the 1 to 20k lookup table range
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um so before it was 1 to 10k it's actually a new
device that pushes us up to the 20k range which is
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pretty unique in uh in the market right now
then traditional fpgas we have a 20 to 55k
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lookup table range a little bit higher
performance fabric more io and uh you
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know some other capabilities that are not on
the non-volatile but you don't get the flash
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so then within that one of the unique things about
going semiconductor is our hybrid fpgas so if you
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see in the part number an s that means that it has
an embedded hardened cortex m3 hardcore processor
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if you see an r in the product name that means
that it has an embedded extended user memory
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and it can be around 4 to 16 megabytes depending
on the device chosen it could have varying bus
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widths and it could be varying types of memory
it can be psram sdram or ddr so you can choose
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the right type of memory for your application
you can also have extended embedded user flash
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e-series is our security fpgas and these
have a puff based embedded security
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core within them and that basically means that
the key generation is asynchronous key generation
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and the keys are generated at power
up based on sram puff technology
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and then we have rf series um gw1 rf series so
if you see a rf in the series name that's an
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fpga plus a hardened mcu and plus a bluetooth low
energy transceiver 5.0 to be specific so hopefully
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that just that's pretty much going semiconductor
product line from the devices in a nutshell
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so now we're going to talk about new and
upcoming semiconductor products so these
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are new devices that are either here now or uh
coming soon so first we have the gw2 an 18x so
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this is an 18k uh it's actually 20k um the the
titles the part number's a little deceiving
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so there's a few extra luts but around a 20k
lookup table device um that's non-volatile
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and it has very fast boot up um from the
embedded flash it has embedded security
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so it has the puff base security and it also has
pin compatibility to other semiconductor devices
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then we have the gw1n2 now this is a 2k
non-volatile device and the key thing about
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it is that it has two gigabit per second rx and
tx mippy d5 hardcores so you have true mippy rx
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at up to two gigabits per second and the speed
on that we know at least uh two and we're
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working to to get a little bit more using the
pre-emphasis capability and then on the tx side
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you have true uh slvs 200 high speed and 1.2 volt
low power mode capabilities to provide a true
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mippy d5 interface so that's really good and also
those uh one and two i believe that there are some
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r series of that so if you need some frame
buffering in there this device is really for
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video bridging and uh video interfacing as well as
some processing and you know it's pretty common to
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sometimes need a frame buffer in those use cases
so the r series is available for that as well
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automotive devices so we have our first automotive
devices and we have a 1k non-volatile as well as a
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20k volatile fpga to kind of cover the automotive
space and these devices are aec100q qualify
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assps so this is something new to go in but
we have a series of application specific chips
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coming out um the first round of them is really
specific to usb to another interface bridging for
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basically programmer cables and programming
so we have a usb to j tag we have a usb to spy
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we have a usb to ur and we have a usb to
is i2c assp so you can look forward to that
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you know there are some of these bridging chips
that are readily available particularly like usb
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to uart just due to programming microcontrollers
but other cases like usb to jtag usb to spy
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and usb to ic there's a lot fewer solutions
on the market and as a result the devices
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are a little bit more expensive so we
think that our assps provide a really
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good um affordable and competitive
competitive solution in the market um
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and so we're really excited about that and
then the last um you know kind of updated
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product um silicon product update is that is the
x series so we have several devices that provide
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pin for pin compatibility to devices that are
either ended end of life long lead time or um
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for customers that are using an existing device
but would like to add some new features some new
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capabilities and they need larger density but
also pin compatibility really is helpful to them
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i need to make one more product update
regarding a legacy device the gw1ns2
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this is different than the gw1n2 that is just
being released with the hardened d5 cores
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the gw1 and s2 was a 2k lookup table fpga with
hardened cortex m3 and hardened usb 2.0 phi
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this device has had some issues related
to the foundry that it was fabricated on
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all of our production devices are fabbed on tsmc
however this other device was was fabricated at a
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different foundry and that led to some issues
so it's been kind of still on the roadmap to
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get it working and it still technically is however
one of the major things that's broken on it is the
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usb 2.0 hard fi in 2.0 mode and we after that
we released a gw1 and s4 which still has the
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hardened cortex m3 but it doesn't have the usb 2.0
hard fi and then now we have the usb 2.0 software
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which works just as well so there's a good chance
that the gw1 and s2 will be discontinued because
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we have the 4k which is an overall lower
cost but more resource intensive device
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and we have the usb 2.0 software solution which
can be used on all of the current go and devices
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so it's very likely that we will discontinue that
device as the two features are already covered in
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a broader spectrum with the tsmc foundry devices
so that's kind of updated semiconductor products
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um from going let's let's go into uh some
solutions update so this is not all of the
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solutions that are kind of coming down the
pipeline but it's a few that i thought were
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notable there's several solutions going on
right now it's pretty exciting what has been
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being developed with our devices and
how much they've matured and advanced
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over the last you know few years so
first is a foc motor control ip solution
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so this is an industrial motor control
solution providing high precision and parallel
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feedback loops for controlling multiple motors you
can show one more or two but one of the you know
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situations that our customers tend to gravitate
towards this solution over other motor control
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solutions is when they run into an issue where
they need to either increase the number of
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i o that the cpu have and particularly
the the types of interfaces so the adcs
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and some of the gpios and encoder links like rs485
i believe they need to increase the number of
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of interfaces for multiple motors and then
also the cpu needs to increase in performance
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to accommodate these motors and typically the
cpu has to kind of dedicate itself to to the to
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each individual motor and give it with a real-time
operating system give it preference and priority
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because if you start running some other
application it starts bogging down the system and
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you don't have a real-time operating system your
motors could start slowing down and going all over
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the place so what the fpga solution provides is an
fpga either in between the cpu and the motors or
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the mosfet drivers or you can actually embed the
cpu inside the fpga and have a one chip solution
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what whatever your preference is um but each motor
control loop runs it completely independently and
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that we provide an api for the cpu to call each
of the current control loop modules so this way
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there's no no bog down on the cpu and the motors
can run independently and when you need to make
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an adjustment that api call just adjusts that
motor and that current control loop in the fpga
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so it's very um good solution and provides a lot
of higher precision control at a i would say a
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much more cost-efficient overall bomb solution
we also have a simple motor control ip this is
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for doing just very simple
motors like maybe in toys or
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consumer applications and we actually have this on
the gw1 and rf so you can actually control a motor
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through bluetooth low energy or multiple motors
for smaller motors for consumer applications so
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that's pretty unique and pretty interesting then
we have go ai 2.0 which is our machine learning
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inference and npu solution and hardware ip so we
have several new demonstrations that have come out
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over the last year person detection car detection
digit detection analog meter detection multiple
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digit detection different input sources so you
know different cameras different hdmi inputs audio
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audio classification gesture control several
demos and there's there's some next generation
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stuff coming that you can look forward to on that
basically mainly around improving performance
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but i would assume some additional
demos that you can look forward to there
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and then lastly the image signal processor ip so
this is if you're if you're not aware when you
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have a system with an image processor sorry
when you have a system with an image sensor
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a lot of times there is not an image
processor built into that image sensor
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so the data that you get from the image sensor is
just raw pixel data and that pixel data needs to
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be processed using an image signal processor now a
lot of times this is built into an soc or you know
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a larger processor device there are dedicated
image signal processors as well but if you're
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doing any sort of image processing on fpga you
need a in a lot of cases you need a image signal
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processor pipeline if you want the image to look
good some cases you don't need it um you know if
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like in the case of go ai if you if you train the
model to accommodate that that you could remove
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those resources and not need the image processor
but in a lot of cases if you're going to output
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that image and use it for something or display
that image coming from the camera you need an
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image signal processing pipeline to make the image
look correct so that's a great new additional iep
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and then the usb 1.1 2.0 and the phi and the sie
so already in ipcor generator within gohan eda
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there's a sie or link layer for usb 1.1
and usb 2.0 and you can either use that sie
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with an external usb 1.1 or 2.05 or an internal
usb 1.0 or 2.05 also within goin ip core generator
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we have a usb 1.1 phi and you can use this on
virtually any of the ios available on any of the
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goin devices and so you can instantiate a usb 1.15
inside the fpga providing a you know link layer
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with the sie and the phi for 1.1 which is
capable of about 12 megabits per second
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lastly what i'm going to go into more detail
is usb 2.0 which is capable of 480 megabits per
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second and this is a really challenging ip to do
and that this is why it hasn't been done before
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it involves clock data recovery at 480 megabits
which is kind of too low for a lot of the
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embedded certes type fpgas but also too fast to
just use gearboxes with over sampling and so we
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have a you know we've built a solution around a
recovery method for the megabit signaling using f
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gowen's dedicated high-speed i o capabilities and
features and that's a patented solution that we're
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really excited about because we've had a number of
requests for usb 2.0 interfacing but haven't been
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able to service them and nobody's really in the
market has been able to service them until now so
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please reach out to your customers if you've had a
customer that has talked about usb and needing usb
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on their products uh we've got we've got the
solution for them and we would really like to
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engage and you know make some opportunities
happen with either usb 1.1 or usb 2.0
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so the usb 2.0 you know the launch
of usb 2.0 phi is on around may 15th
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of 2021 and you'll probably be seeing this
presentation around then so at that time the
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latest version of going eda with ipcor generator
will have the usb 2.0 softfi available for use
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in in the eda tool so it's already ready to go and
you can virtually again with a few limitations on
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the 2.0 because you need to use the the high speed
io but virtually any io any fpga that gowan has an
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offering for you can use the usb 2.0 software so
you can have multiple usb 2.05 no problem there
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so here's a little bit more focused update going
is now a member of the usb implementers forum and
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we have 1.1 and 2.0 solutions so 12 megabits
per second and 480 megabits per second 1.1
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is still used a lot for control and just basic
communications and actually usb 1.1 is kind of
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included with 2.0 so so 2.0 is actually capable
of a 12 megabit mode and a 480 megabit mode
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usb 2 generally has applications that are more
data transfer specific since the data rate is up
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um so in ipcor generator we have all
these ips the 1.15 2.05 1.1 and 2.0 sie
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and it's kind of defaulted to a virtual com port
scenario but you can use it for other things
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we just use that example because it's uh we like
the virtual com port because there are native
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drivers within windows 10 windows 7 windows 10 and
linux that makes it very easy to just get started
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and i'll explain a little bit more about that
later we also have a usb type-c power delivery
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solution and so you can actually you know if
you have customers that are interested in us
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usb or usb type-c you can actually combine these
ips together for uh you know a total usb solution
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and then lastly we support primarily
just out of the box the virtual comport
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type solution because again it's the the
driver capability makes it very easy to use
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however there are other device types being
explored like video over usb things like that
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and that will just basically as as the solutions
build there will be more um more device types
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and you can program these for different
device types that the si is fully programmable
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so lots of good opportunities
there for new and unique solutions
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okay so now uh we're going to go into just
specifically usb 2.0 finesse ie so this is again
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a brand new solution to the fpga market previously
before this solution that only gowan has
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you had to use an external phi to interface a
separate chip to interface the uh to interface usb
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2.0 with an fpga and there's a patent
pen pending implementation for this
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that is uniquely capable on gowen's
high speed and flexible fpga i o
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supported in all going devices um with exception
to the 1nz which is our ultra low power device
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it has overall lower performance so
that just due to its low power and
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so that one's not supported but everything else
is and then devices can support as many usb 2.0
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interfaces as the i o permits so that means that
you can do things like a usb hub uh you could do
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a hub of you know usb to pcie you could or you
could do or sorry excuse me a pci you could do a
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you know you could do the the possibilities are
pretty much endless you can do microphone to usb
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you could do multiple microphones to usb you could
do um usb to device to usb host you could do hsic
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to usb there are many options and this is just
an interface to allow customers to be creative
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with whatever they want to build so now
i'm going to go into usb 2.0 phi and sie
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just some information related to it so the usb
2.0 and 1.05 run at 60 megahertz this is native to
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the deserialization process and the over sampling
process that's pretty common with all usb
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utmi interface fis as well as the sies and
then just 2.0 runs faster so 480 megabits
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and usb 1.1 at 12 megabits the resources for
the 2.0 are a little bit larger just under 2k
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lookup tables so this can fit in as small as a
2k device and uses five block ram versus the 1.1
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solution which is three block ram so you know i
just mentioned this so if you have like a really
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tight or cost you know sensitive solution we have
a we've had a lot of customers before we even had
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the usb 2.0 solution they would come to us and
say i need a usb 2.0 solution and a lot of them
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as we started to communicate with them they
just needed a usb 2.0 solution for basic control
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and communication they didn't need the full 480
megabits and there are some i o advantages and
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some resource advantages to the 1.1 solution so if
you just need 12 megabits go with the 1.1 solution
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don't don't go beyond that and so i would say a
lot of there is a lot of customer opportunity just
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for the usb 1.1 solution and then if you need the
extra bandwidth 2.0 is available and this is just
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a block diagram of what um what the fi and the sae
look like you know if you were to place both ips
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in the fpga and we do have a reference design for
this and basically the phi and the usb sie talk
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over a utmi plus interface which is the common
interface between the phi and the link layer
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okay usb solution roadmap so 1.1 is available
now 2.05 is just released and these are the
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eda numbers that it should be the sie for 2.0 and
1.1 is available now we have reference designs
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for virtual com ports virtual com port device id
and then we have a video video over usb solution
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that we're working on and then you can expect
other protocols and other examples to follow
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we also are working on a csi2 mipi csi2 camera to
usb 2 reference design so this should be pretty
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unique and pretty cool kick off about for this
is mid main you should expect it sometime in q3
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we also have an hsic reference design in progress
so hsic is basically usb 2.0 for inside inside
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embedded devices so it's basically kind of like
usb 2 but inside like let's say a pc and the
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benefit of using hsic is that it provides a clock
lane so you don't need the clock data recovery
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so it's kind of similar to like mipi csi 2 if
you're familiar with that protocol or maybe dsi or
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maybe d5 and this provides both a power and a cost
and a ease of use benefit for situations inside
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on on ship or on the board so that's it's used
for things like inside a pc however once you go
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outside the pc and you're going over a cable you
can't really send a clock and data over wire pairs
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over a cable things get out of alignment and even
if you have alignment capabilities there can be
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you know uh issues with the uh the peak to peak
voltage being reduced and things like that so you
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need a little bit more advanced recovery system
and so it's best to use fewer wires which just
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makes the cable cheaper and embed the
clock within the data which also helps
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with the voltage levels um if the data basically
in the when the when the clock is encoded
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in the data the way that it's encoded means that
there's an equal balance of zeros and ones which
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means that the peak-to-peak voltage doesn't drift
and that's that's the benefit and that's why
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we typically use embedded clock on
cable interfacing so but there's a
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lot of opportunities for going from hsic for
communication inside on the pcb and then going
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out on a cable with usb 2.0 and so that's
exactly why we're building that reference design
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so mainly on the usb sie side we have the
device side so it's just a more popular use case
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however we have basically for our testing purposes
we have the the code to do a host solution as well
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so this would be you'd use the
same fi but you'd be able to do
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a host link layer and communicate with usb devices
so this in progress is a little further out but
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q4 around that time frame of this year please
let me know if you see any usb 1.1 or 2.0 host
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solution needs and we can communicate
and talk about that and see
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see make sure we understand their needs and make
sure it's aligned with that target completion date
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lastly we have an mjpeg encoder and this is
in progress uh you know sometime around the q4
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time range this is needed for things like uh
the csi2 to usb solution um or it may be so
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we have it kind of on the roadmap that
it's something that we'd like to do we see
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you know some need and if you see any
you know use cases or opportunities there
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related or not related to usb please let
us know and we will try to understand those
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00:31:45,680 --> 00:31:51,120
customers needs as best as possible and
adjust our solution roadmap accordingly
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and then also the bridging assps which i talked
about earlier these are application specific chips
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that just do the function they do so usb
to jtag usb to spy usb to i2c usb to ur and
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i2s audio to and from usb you can expect these
around the q3 time frame and they're they're
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currently in testing and so i think that that
that's where on the timeframe will be available
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okay so now i'm going to go into use cases now i
have to make it clear that some of these are will
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be available and some of them are just theoretical
use cases to start engaging with customers um the
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00:32:38,960 --> 00:32:48,560
big feat has been conquered which was to get the
usb 1.1 and 2.0 solutions available but now we're
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00:32:48,560 --> 00:32:54,560
gonna go into you know what you could use it for
and some of these are built like the example here
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00:32:54,560 --> 00:33:08,080
for usb bridging so usb to jtag usb to spy usb
to i2c usb to ur and i2s audio to and from usb
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00:33:08,960 --> 00:33:16,400
so yeah this is just a high level diagram of those
same use cases as the assp but we also have them
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in fpga solutions as well in case a customer wants
to expand add some buffering some extra features
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00:33:25,920 --> 00:33:35,280
another usb example is the usb sorry csi2 to usb
solution so here's a diagram of that and then also
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usb to dsi so let's say you have a small display
and you want to interface to that display over
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over usb that's also possible and that solution
we don't have you know it's not on the roadmap but
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if you if you see a customer that is interested
in that we can certainly discuss that with them
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00:33:59,280 --> 00:34:08,000
okay usb to bluetooth examples so going to or
from bluetooth low energy since we have the gw1 rf
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00:34:08,000 --> 00:34:16,800
device you can definitely make a usb to bluetooth
low energy dongle so that's pretty unique and this
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00:34:16,800 --> 00:34:21,440
solution is is not something that's on the roadmap
but would be actually fairly straightforward to
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00:34:21,440 --> 00:34:26,480
put together i think so please let us know
if you see any opportunities in this area
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00:34:29,840 --> 00:34:36,880
data and storage buffering so sorry data
shortage and buffering these are just a couple
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00:34:37,520 --> 00:34:45,040
kind of high-level solution ideas so the one
on the left the diagram on the left is showing
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basically using the embedded user flash of the
little b product family the non-volatile family
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and use utilizing that that internal flash to
connect to usb 2.0 and so this could be used for
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00:35:01,760 --> 00:35:06,000
let's say security dongles where you may have some
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some key pair in the flash you could also
use this with our secure fpga solution
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and this would basically provide a non-volatile
region that you could access over usb 2.0
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and then on the right side this is
taking advantage of the extended ps ram
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devices the r series devices i mentioned earlier
and it's just showing that you know you got four
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to eight megabytes of extended ps ram memory in
the fpga you could also interface to external
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00:35:40,480 --> 00:35:47,840
memories with the goin device like ddr and you
could have some input data you could buffer it
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and then read it out of usb2 at your own pace
or time depending on the application so this is
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00:35:54,240 --> 00:36:01,040
pretty interesting could be very useful for data
acquisition like data acquisition cards if you've
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got you know a bunch of wires monitoring some
system you can store it and then buffer it out
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have it buffered and then read
it out on the pc win as needed
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this is kind of another idea of a traffic monitor
kind of similar to the data buffering case
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where um you basically just have
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a usb to usb passthrough but then you can monitor
the usb traffic and particular usb data and
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this can be you know really useful as as
a usb snooper line snooper and in fact
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you know i use this a lot during deep when i
was debugging um or testing the usb 2.0 solution
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but um this can uh you you don't even need
to build a gui for this um you can actually
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just use goin's gau going analyzer oscilloscope
so it's our built-in fpga logic analyzer you can
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just use that to monitor the data and actually
record it and save it to a file so for you know
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debugging solutions traffic monitoring solutions
over usb 2.0 this is a great uh offering
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00:37:29,600 --> 00:37:35,840
so lastly is kind of the the multi-port hub
concept so as i mentioned you can have multiple
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usb phi interfaces and so using the host solution
that's on the roadmap along with the device
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00:37:44,320 --> 00:37:51,760
solution this allows you to do usb hub and one
thing i left out is there's also opportunity to do
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usb hsic for the device interface and then go
out to multiple usb hosts as well so true usb
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hub chip and you can make all of the
virtual types of channels and that you want
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okay so those are my my kind of high level use
case get your ideas flowing examples and now
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00:38:18,000 --> 00:38:23,840
i'll talk a little bit about how you can actually
have customers test these examples and get started
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00:38:24,560 --> 00:38:30,400
so um the the usb 2.0 solution as
well as the 1.1 solution are are
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very um robust at this point i feel and uh we
do have a production board that is actually our
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00:38:39,520 --> 00:38:46,720
dk start gw2a18 board that has been modified
just one of the connectors has been removed
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and it's been replaced with the usb 2.0 port
running to the fpga and you can do usb 2.0 or
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00:38:53,840 --> 00:39:00,000
1.1 with this right now the board is in very
limited supply because we had just our first
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00:39:00,000 --> 00:39:07,200
test run of the boards but it does work and if you
know there is a high customer need we can get you
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one of those boards temporarily and then we have
production availability of that this board around
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june 15th so you can expect it on the website
you can expect it um through your distribution
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00:39:23,520 --> 00:39:29,520
abilities to obtain it and then uh there
also is another internal board that has
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00:39:29,520 --> 00:39:36,480
just arrived internally and i there is limited
supply but it's another option the nice thing
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about this board is that it has a little b and
aurora device on it so if you have a customer
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00:39:42,560 --> 00:39:50,640
that may want to focus on little b um we're doing
that validation as well this board is also in very
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00:39:50,640 --> 00:39:56,240
limited supply but we can make exceptions
for particular opportunities that may arise
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so in addition to all of this we're building up
the go in design services capabilities um a lot
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00:40:11,920 --> 00:40:20,400
and so going i call it gds and we're kind of
expanding on this is going design services
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00:40:20,400 --> 00:40:26,800
it's our applications engineering team providing
design services for customers that want to build
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00:40:27,680 --> 00:40:34,080
application specific solutions and
they need some design consultations to
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00:40:34,080 --> 00:40:41,360
get them there maybe they're not so familiar with
fpgas maybe they're a little uncomfortable because
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00:40:41,360 --> 00:40:46,960
they've never used going fpgas before and they
need a little it could be as simple as just hand
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00:40:46,960 --> 00:40:52,800
holding some some support to get started it could
be as extreme as doing the whole design for them
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00:40:52,800 --> 00:41:02,560
and so we're building up a platform to provide
this capability so providing custom application
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00:41:02,560 --> 00:41:07,680
specific design consultation and providing
hardware as a service is what we like to call it
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00:41:08,240 --> 00:41:16,000
and uh so as of right now you can it's you
will see this expanding over the next year
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00:41:16,000 --> 00:41:21,520
but for now we're just basically going
through the info at go on semi email and so
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00:41:21,520 --> 00:41:26,720
any potential design requests you want to submit
you can either submit them to your go in sales
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00:41:28,080 --> 00:41:35,840
sales director directly or you can send them
through info go on semi.com you can also just
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00:41:35,840 --> 00:41:44,400
send them to me i have no problem with that and uh
you can also you know i just put the distribution
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00:41:44,400 --> 00:41:52,400
page which has access to um you know many of the
distributors and reps that may also be able to
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00:41:52,400 --> 00:41:58,800
community support you or at least i put
this here just in case this presentation
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00:41:59,520 --> 00:42:07,040
has a derivative customer facing presentation
and this would provide them the access point to
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00:42:07,680 --> 00:42:16,960
communicate with you the distributors or the reps
and then for any design service just be ready to
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00:42:16,960 --> 00:42:22,320
provide us the following we're going to be asking
for it if you send us an email without it so
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00:42:22,320 --> 00:42:27,520
we need to know the design requirements as
detailed as you can possibly do and one thing
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00:42:27,520 --> 00:42:33,440
that's very very very helpful that is a lot of
times missing is a technical block diagram if
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00:42:33,440 --> 00:42:38,560
you can draw a block diagram of it it provides
us a picture of what you want it's very helpful
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00:42:39,520 --> 00:42:45,200
also you know on the design requirements one
thing that can sometimes be missing as the speeds
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00:42:45,200 --> 00:42:52,000
that things need to run at that's also useful and
anything you can provide a little bit at a higher
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00:42:52,000 --> 00:42:58,560
level about the application like if it's using
2.0 what is it interfacing too is it a computer
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00:42:59,360 --> 00:43:03,840
what kind of data are they going to send things
like that the more information the better
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00:43:04,640 --> 00:43:12,640
projected volume is really important for us
because it helps us determine our nre structure so
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00:43:14,480 --> 00:43:18,400
i don't think most customers don't have a problem
with what they're projecting if you could provide
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00:43:18,400 --> 00:43:26,400
that that would be great and then estimated nre
budget for design development so we really want
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00:43:26,400 --> 00:43:35,680
to get into the habit of asking this question
because it's often not asked and then it becomes
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00:43:35,680 --> 00:43:44,960
you know potentially an issue later so you know
you we've got a customer opportunity it comes
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00:43:44,960 --> 00:43:52,080
into sales we have apps engineers that spend time
to research and and and understand the solution
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00:43:52,080 --> 00:43:56,880
that needs to be developed and maybe does some
pre-development to make sure that we can do it
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00:43:57,440 --> 00:44:03,440
and then they come back and say yep we can do it
um how big is the volume you know if the volume
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00:44:03,440 --> 00:44:11,360
is small then uh we request the nre and the
customer i think feels kind of um a little bit
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00:44:12,000 --> 00:44:19,680
uh blindsided at that point so we i just
appreciate if we can get into the habit of just
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00:44:19,680 --> 00:44:26,000
asking um you know do you have an nre estimate
for doing this design for you and if you know if
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00:44:26,000 --> 00:44:30,160
there's hesitation we say well based on the volume
you know we might not even need it or based on the
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00:44:30,160 --> 00:44:37,040
roadmap it might be already something we're doing
but we do need to ask because we do spend a lot
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00:44:37,040 --> 00:44:44,880
of r d budget to to develop these designs and
sometimes you know plans change projects change
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00:44:45,440 --> 00:44:52,640
so if you could help us help you by just asking
this question up front it'd be very helpful
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00:44:55,280 --> 00:45:00,560
and then other resources so if you're new
to usb or want to understand more educate
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00:45:00,560 --> 00:45:09,280
yourself i highly recommend this usb made simple
website it is great it goes through usb 1.1
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00:45:09,280 --> 00:45:15,280
2.0 it goes through things that i always refer
back to it there's things that i still don't
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00:45:15,280 --> 00:45:20,960
know about usb and it is on the site so i highly
recommend it if customer has some questions or
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00:45:20,960 --> 00:45:27,920
you know thoughts it's a great great site to
utilize also the usb 2.0 specification itself
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00:45:27,920 --> 00:45:34,640
itself is available for free and the usb utmi
interface specification is also available
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00:45:36,160 --> 00:45:43,120
there are some things i will say that the usb utmi
interface that's the interface between the phi
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00:45:43,120 --> 00:45:50,960
and the link layer that are discussed in the utmi
specification that i feel are vague in the 2.0
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00:45:50,960 --> 00:45:58,560
specification and vice versa so um i would if you
know i would provide both um to your customer at
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00:45:58,560 --> 00:46:04,240
the same time and if you're educating yourself
i would look at both and then below i just have
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00:46:04,240 --> 00:46:10,320
the social media pages for going something that
your customers can reference i do intend to make a
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00:46:10,320 --> 00:46:18,640
customer friendly version of this presentation and
video so um that's kind of why it's there and you
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00:46:18,640 --> 00:46:25,680
can expect that there will probably be some usb
demo videos available and there also is a quick
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00:46:25,680 --> 00:46:37,360
start guide for the dkstart uh dk dkstar ar18 usb
board so that's a starter guide that allows you to
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do a virtual com port data loop so you send data
to the host and then you receive it back and then
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00:46:49,440 --> 00:46:55,200
it also if you press numbers it will light up
leds so if you press numbers on the keyboard
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00:46:55,200 --> 00:47:01,360
it will light up a corresponding led and then also
if you push push buttons on the board it will send
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00:47:01,360 --> 00:47:08,240
a message back to the pc so pretty basic but
pretty cool demo and that's all running at 2.0
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00:47:09,200 --> 00:47:12,800
and that you could also do it with
1.1 we're not pushing the performance
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00:47:13,440 --> 00:47:19,440
the performance is native to the protocol when
you're in each mode so basically if you go into
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00:47:19,440 --> 00:47:26,960
2.0 the packets just transfer faster that's it
for me i hope this was useful please let me know
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00:47:26,960 --> 00:47:32,080
what i could add or subtract particularly for
the customer facing presentation version of
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00:47:32,080 --> 00:47:39,040
this and i look forward to helping you go in
by programming for the future thanks a lot
48320
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